• Bangalore - 560076
  • 8904740434
  • learn@techieventures.in

VLSI training institute in btm layout

Description

Since VLSI is a niche industry, skill-sets in this industry are short in supply and therefore in great demand. Hence there is tremendous scope and growth in this field.

According to industry experts, the Indian VLSI industry requires anywhere between 10,000 and 20,000 highly trained engineers at present. And to ignite your adrenaline rush, this is the highly paid industry in engineering sector.

Duration
  • 1) VLSI Design and Verification (Front- End)4 months.
  • 2) Only Verification 2 months.
  • 3) VLSI Industry standard projects 2 months.
  • 4) VLSI vacation course. 1.5 months.
Career Option
  • VLSI / ASIC / Soc Design and Verification Engineer
  • ASIC Verification Engineer.
Opportunies

In the total span of, from design to fabrication, 80% of time is spent over verification. So there are tremendous opportunities in India and abroad for VLSI design and verification. So why are you still waiting, go grab the opportunity to fulfill your dream job !!

Major Companies Using VLSI
  • Intel
  • QUALCOMM
  • Broadcom
  • IBM
  • hundreds of semiconductor industries.
  • In India 90% of VLSI companies are hailed in Bangalore.

Course Content

Course: VLSI Design and Verification (4 months)

Course: VLSI Design and Verification (4 months)
Basic Electronics
Basic application of Diode, BJT, JFET, MOSFETs
Introduction to CMOS
Basic circuit design with CMOS
Current nanometer technology
Currently proposed semiconductor devices( FinFET, TFET, IMOS, CNTFET, etc)

Digital Design

Number System and Codes
Logic Gates and Boolean Algebra
Combinational Logic Circuits
Flip-Flops and Related Devices
Counter and Registers
FSM Design
Timing Analysis
VLSI Logic Circuits
Memory Devices

Verilog

Overview of Digital Design with Verilog HDL
Hierarchical Modeling Concepts
Basic Concepts
Modules and Ports
Gate-Level Modeling
Behavioral Modeling
Task and Functions
FSM Design
Useful Modeling Techniques
Mini Project

System Verilog

Introduction to system Verilog
Object oriented Programming
Threads and virtual Interfaces
Functional coverage
Verification planning
Advanced system Verilog
Assertion based verification
Verification mini project

UVM

Introduction to UVM Methodology
UVM TB Architecture
Stimulus modeling
Creating environment
UVM simulation phases
Testcase classes
TLM overview
Configuring TB environment
UVM Sequences and Sequencers
Creating TB Infrastructure
Building scoreboard
Building reusable environments

Course: VLSI Verification
System Verilog

Introduction to system Verilog
Object oriented Programming
Threads and virtual Interfaces
Functional coverage
Verification planning
Advanced system Verilog
Assertion based verification
Verification mini project

VLSI Design and Verification Project
GPIO design and verification
SPI design and verification
UART design and verification
Ethernet design and verification
AMBA-AXI design and verification
AMBA-APB design and verification
AMBA-AHB design and verification DDR design and verification